Pinch-off type vertical junction field effect transistor and method of manufacturing the same

ABSTRACT

A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region ( 2 ) of a second conductivity type provided on a surface of a semiconductor substrate, a source region ( 1 ) of a first conductivity type, a channel region ( 10 ) of the first conductivity type that adjoins the source region, a confining region ( 5 ) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region ( 3 ) of the first conductivity type provided on a reverse face, and a drift region ( 4 ) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.

This application is a national phase of PCT/JP00/06211 filed on Sep. 11,2000, under 35 U.S.C. § 371.

TECHNICAL FIELD

The present invention relates to a junction field effect transistor(JFET) that performs a high current, high voltage switching operationused in a direct current/alternating current conversion in powertransmission and in an inverter and the like, and more specifically, toa vertical JFET that achieves further reduction in the power loss.

BACKGROUND ART

A junction field effect transistor (JFET) used for switching of aninverter and the like is required to endure high current and highvoltage. FIG. 25 is a diagram representing a normal horizontal JFET. Inthe horizontal JFET, carriers move substantially parallel to thesemiconductor substrate surface. A ground potential is applied to asource region 101 through a source electrode 111, and a positivepotential is applied to a drain region 103 through a drain electrode113. A pn junction is formed below a gate region 102 beneath gateelectrode 112, and when the device is caused to attain an off-state, anegative voltage is applied to gate electrode 112 such that thisjunction portion attains the reverse bias state. When the device is inan on-state, electrons in source region 101 are attracted by thepositive potential of drain region 103, pass through a channel region110 under gate region 102, and reach drain region 103.

In the above-described horizontal JFET, the source electrode, the gateelectrode, and the drain electrode are located in the same plane asshown in FIG. 25 so that the drain electrode and other electrodes wouldbe close with air existing therebetween. Since breakdown electric fieldof air is 3 kV/mm at most, there was a need to place the drain electrodeaway from other electrodes by at least 1 mm when a voltage of 3 kV orgreater was applied between the drain electrode and other electrodes inthe off-state in which no current flowed. Consequently, the length of achannel region 109 leading from source region 101 to drain region 103became long, and only a small current could be allowed to flow, so thata high current required for a so-called power transistor could not beallowed to flow.

FIG. 26 is a diagram representing a vertical JFET, also called a staticinduction transistor (hereinafter, referred to as an SIT), that isproposed and practically utilized so as to provide improvement upon theweakness of the above-described horizontal JFET. Unlike the horizontalJFET, the carriers move substantially in the direction of thickness ofthe semiconductor substrate in the vertical JFET. In an SIT, a pluralityof gate regions 102 are formed as p⁺ regions in which p type impurity ofhigh concentration is implanted, and n⁻ region having n type impurity oflow concentration added is formed therearound. Since the n type impurityconcentration in the n⁻ region is low, a depletion layer expands at alltimes and the channel region is vanished. As a result, the saturationphenomenon of a drain current due to a pinch-off that occurs in theabove-described horizontal JFET does not take place. The method ofpotential application to each of the source region, the gate region, andthe drain region is the same as that of the horizontal JFET shown inFIG. 25. The electrons in source region 101 overcome the potentialbarrier of the gate region, are attracted to the drain potential, anddrift in the depletion layer. When the drain potential is set to a highpositive potential, the potential barrier against the electrons of thegate region becomes small, which allows an increase in a drift current.Thus, the saturation phenomenon of the drain current would not takeplace even when the drain potential is raised. The drain current isnormally controlled by a gate potential and a drain potential. When theabove-described SIT is utilized for switching, in order to obtain alarge current, the voltage had to be set high so as to allow theelectrons to overcome the potential barrier, which inevitably resultedin a certain loss, though small.

Moreover, when a JFET was caused to attain the off-state in theswitching operation, there was a need to apply a negative voltage whoseabsolute value exceeded 10V to a gate electrode in order to pinch offthe channel region with the depletion layer. Since the application ofsuch negative voltage having a large absolute value causes power lossalso in the off-state, it is desirable to realize the off-state withoutany power loss.

Furthermore, in general, the impurity concentration of a channel regionin a JFET is subjected to restrictions in order to ensure a prescribedtransistor characteristic, so that it cannot be set too high.Consequently, the electric resistance of the channel region tends toincrease, and what is more, the electric resistance varies according tothe impurity concentration, the thickness of the channel region, and soon. The transistor characteristic is strongly influenced by the electricresistance of the above-described channel region so that it variessignificantly according to the variations in the impurity concentration,the thickness and the like. If, in order to avoid such variations ateach devices, an impurity element of a high concentration is implantedfor the purpose of reducing the electric resistance in the channelregion, the withstand voltage performance would be degraded. Thus, therewas a demand for a JFET that has the reduced on-resistance without theuse of an impurity of a high concentration and that is less likely to beaffected by variations in the impurity concentration of the channelregion, the thickness of the channel region, and so on.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide a JFET that is capableof a high withstand voltage, high current switching operation and thatoperates with a low loss. Moreover, another object of the presentinvention is to provide as a power switching device a powersemiconductor device that is capable of reducing the voltage required tocause the off-state in order to realize an even lower loss. In addition,a further object of the present invention is to provide a JFET that hasa superior withstand voltage performance and a low on-resistance andthat is less likely to be affected by variations in the impurityconcentration and the thickness of the channel region, and so on.

A JFET according to the present invention is provided with a gate regionof a second conductivity type provided on one main surface of asemiconductor thin body, a source region of a first conductivity typeprovided on the one main surface side, a channel region of the firstconductivity type that adjoins the source region, and a confining regionof the second conductivity type that adjoins the gate region andconfines a range of the channel region. The JFET is further providedwith a drain region of the first conductivity type provided on the othermain surface of the semiconductor thin body, and a drift region of thefirst conductivity type that continuously lies in a direction ofthickness of the semiconductor thin body from the channel region to thedrain region. In this JFET, a concentration of an impurity of the firstconductivity type in the drift region and the channel region is lowerthan a concentration of an impurity of the first conductivity type inthe source region and the drain region and a concentration of animpurity of the second conductivity type in the confining region.

According to this arrangement, in the off-state, a reverse bias voltagecan be applied to the gate region to form a depletion layer from theconfining region toward the channel region so as to block the flow ofcarriers that passes from the source region via the channel region andthe drift region toward the drain region. Moreover, application of ahigh voltage to the drain region in the off-state results in applicationof a high reverse bias voltage to an interface between the confiningregion and the drift region so that a depletion layer is formed from theconfining region to the drift region. At this time, this depletion layerinterposed between the drain region and the gate region withstands thevoltage so that the withstand voltage performance between the drainregion and the gate region can be improved. In addition, in theon-state, the source region and the gate region are brought to about thesame potential so as not to allow the formation of the depletion layer,while allowing carriers to move from the source region via the channelregion and the drift region to the drain region. The amount of carriermovement, or the current, is controlled by the drain potential. As thedrain potential is raised, it becomes a pinch-off potential, and thedepletion layer begins to expand from the interface between theconfining region and the drift region toward the drift region, wherebythe drain current becomes saturated. Such an operation is essentiallydifferent from the operation of a conventional vertical JFET (SIT) inwhich there is no pinch-off and saturation of the drain current does notoccur. The improvement of the withstand voltage performance due to thedepletion layer withstanding the voltage in the off-state describedabove, the saturation phenomenon of the drain current in the on-state ina case where a current flows in the direction of thickness of thesubstrate, i.e., vertically, and so on are operations that have onlybecome possible with the JFET of the present invention. By thesaturation of the drain current described above, the burnout of the JFETitself and the surrounding elements can be prevented. It is to be notedthat there is nothing to prevent the flow of the carriers in a pathleading from the source region to the drain region in the on-state,which achieves an extremely low on-resistance. Thus, the powerconsumption can be further reduced when compared with the conventionalSIT and the like in which the carriers are forced to pass through thepotential barrier in the depletion layer.

Moreover, here, in the case where the first conductivity type impurityand the second conductivity type impurity are included, the impurityconcentration would indicate, unless otherwise noted, the concentrationof the dominant impurity that remains after the impurities cancel oneanother out.

In addition, in the above-described JFET of the present invention, thegate electrode making contact with the gate region preferably forms anohmic contact with the gate region. With the ohmic contact, it becomespossible to project a depletion layer from the confining region towardthe channel region in the interface between confining region and channelregion forming a pn junction to realize the off-state with highcontrollability by the application of a reverse bias voltage to the gateelectrode. Since the second conductivity type impurity concentration ofthe gate region is high, it is easy to provide the ohmic contact.

According to the above-described JFET of the present invention, wherethe simplicity of the structure becomes important, the confining regionpreferably confines and encloses the gate region from an inner side ofthe semiconductor thin body, for instance.

With this arrangement, since the confining region is formed such that itconfines and encloses the gate region from an inner side, thearrangement is simplified and the number of mask forming steps duringmanufacture is reduced so that the manufacture is facilitated, therebyimproved yield is achieved. In addition, the gate region contains animpurity element of the same conductivity type as that of the confiningregion, and a depletion layer can be projected from the confining regiontoward the channel region to realize the off-state. Moreover, in thisoff-state, when a high voltage is applied to the drain region, a highreverse bias voltage would be applied to the interface between theconfining region and the drift region, and the depletion layer is formedfrom the confining region to the drift region and withstands the voltagebetween the drain and the gate so that the withstand voltage performancecan be improved.

In the above-described JFET according to the present invention, the gateregion coincides with the confining region.

When the confining region is confined in the vicinity of a surface ofthe substrate, there is no need to distinguish the confining region fromthe gate region either in spatial dimensions or in impurityconcentration, and they coincide. In such an arrangement, the structureis simple so that the manufacture is facilitated. Moreover, the term“gate region” may refer to a region of the second conductivity typeformed in a position deep into the direction of thickness of thesemiconductor thin body which surpasses the range of the gate region inthe usual sense of the term, that is, a semiconductor region of thesecond conductivity type with which a gate electrode makes ohmiccontact. When the range of the gate region is thus spread, the confiningregion and the gate region always coincide. In the present description,however, the region that encloses and confines the channel region willbe referred to as the confining region regardless of the position beingdeep or shallow in the semiconductor thin body. The term gate regionwill be used in the usual sense of the term to mean the region in avicinity below the gate electrode where the gate electrode makes ohmiccontact.

In the above-described JFET according to the present invention, thesource region is preferably formed protruding from one main surface andthe channel region is formed beneath the source region in a continuousmanner.

With this arrangement, the mask utilized for patterning of the sourceregion using dry etching can be also utilized for the implantation of asecond conductivity type impurity element into the gate region and theconfining region enclosing the gate region. As a result, the number ofmasking steps can be reduced and the mask alignment is facilitated, sothat improvement in the yield can be achieved.

In the above-described JFET according to the present invention, the gateregion is formed of two regions, these two gate regions are respectivelyconfined and enclosed by the confining regions, and the channel regionis disposed in contact with and between these two confining regions.

With this arrangement, the structure of the JFET becomes even simplerand the mask alignment is facilitated, which contributes to the effectof reduction in the number of manufacturing steps as well as to theimprovement in the yield.

In the above-described JFET according to the present invention, a widthof the channel region enclosed by the confining region is smaller than athickness of a depletion layer due to a built-in potential in a junctionportion between the confining region and the channel region.

Normally, a JFET attains the on-state when no voltage is applied to thegate electrode and attains the off-state when a negative potential ofwhich absolute value exceeds 10V is applied to the gate electrode. Inother words, a JFET commonly performs a normally-on operation. When theJFET of the normally-on type is used for the control of a motor and thelike, since the on-state is attained when no voltage is applied to thegate electrode, the motor would remain in rotation in the case of a gatefailure, which is dangerous. Consequently, when the JFET of thenormally-on type is used for the control of the motor and the like, inpreparation for an instance of failure, there is a need to provide amechanism to a gate circuit to turn itself off when it fails, whichcomplicates the gate circuit arrangement. Moreover, power consumptiontakes place even during the off period since there is a need to continuethe application of a negative voltage in the off-state.

With the above-described arrangement, the JFET of the present inventionbecomes a normally-off type. In other words, the off-state is realizedwhen no voltage is applied to a gate, and the on-state is attained whena relatively low positive potential is applied to the gate. By utilizingthis normally-off type JFET, the control of the motor and the like canbe performed without providing the gate circuit with a mechanism toremedy the failure. Moreover, power consumption does not take placeduring the off period.

In the above-described JFET according to the present invention, a firstconductivity type impurity concentration of the drift region ispreferably higher than a first conductivity type impurity concentrationof the channel region.

With this concentration arrangement, when the off-state is to beattained, a reverse bias voltage can be applied to the gate electrode toensure the projection of the depletion layer toward the channel region.Thus, the off-state can be realized with certainty and with high speed.When the on-state is to be attained, the depletion layer can be vanishedin a short period of time so that a high-speed switching becomespossible. In addition, the first conductivity type impurityconcentration of the drift region is lower than the second conductivitytype impurity concentration of the confining region, so that a depletionlayer is also formed in the drift region along with increase in thereverse bias voltage, and this depletion layer contributes to withstandvoltage, thereby achieving higher withstand voltage performance. Whenthe drain voltage is raised in the on-state, the depletion layer expandsfrom the confining region toward the drift region, causing a pinch-off,and the drain current is saturated so that problems such as burnout canbe prevented.

In the above-described JFET according to the present invention, aninterposed region of the second conductivity type is provided that makescontact with a source electrode located on the source region and thatpasses through the source region and stretches out to the channelregion.

With this structure, an electric field within the channel regiondirected from a portion of the confining region close to the sourceregion toward the source region can be increased. Consequently, thedepletion layer that expands from the interface between the confiningregion and channel region toward the channel region readily spreadstoward the source region. As a result, the off-state can be realizedwithout applying a large negative voltage between the source and thegate so that it becomes possible to achieve an even lower loss as apower switching device.

In the above-described JFET according to the present invention, theinterposed region may have an arrangement of being separated into atleast two regions with a region of the first conductivity typesandwiched therebetween.

With the above-described structure, it becomes even easier for thedepletion layer to expand from the interface between the confiningregion and channel region toward the source electrode side so that theoff-state can be achieved with a negative voltage whose absolute valueis low. The at least two regions described above may be flat plate-likeor column-like in shape.

In the above-described JFET according to the present invention, theoverall channel region may include a low impurity concentration regionor portion of the first conductivity type provided within the overallchannel region, which is in contact with the confining region and thesource region. The low impurity concentration region or portion has aconcentration lower than a concentration of an impurity of the firstconductivity type in a remaining channel portion of the overall channelregion.

The depletion layer expands long from the interface between theconfining region and the channel region, on the channel region sideapproximately in proportion to the ratio of the concentration of animpurity of the second conductivity type of the confining region to theconcentration of an impurity of the first conductivity type of thechannel region. In other words, the depletion layer expands long towardthe side on which the impurity concentration is low, approximately inproportion to the ratio of the impurity concentration. Consequently, byproviding the low impurity concentration region, portion it becomespossible, with a low reverse bias voltage, to expand the depletionlayers even longer to allow the depletion layers expanding from theconfining regions on either side to combine and to realize theoff-state. In other words, it becomes possible to combine the depletionlayers on either side with a negative voltage having a smaller absolutevalue so as to shut off the passage of charge carriers.

In the above-described JFET according to the present invention, thesource region and the channel region are both separated into tworegions, and a conductive film is provided which is sandwiched betweenthe two channel regions in a position range that is lower than a topsurface level of the channel region.

With the above-described arrangement, the electric resistance of a drift(channel) path that extends in the direction of thickness of thesubstrate from the two source regions provided on the one surface (frontface) side toward the drain region on the other surface (reversesurface) of the semiconductor substrate becomes small. Thus, a portionon which the conductive film is formed with respect to the pathpartially forms a parallel circuit with respect to the path. Asdescribed above, in the case of a JFET in which carriers flow in thedirection of thickness of the substrate, it becomes possiblesubstantially to reduce the electric resistance of the channel regionthat lies along in the direction of thickness. Consequently, it becomespossible to achieve high withstand voltage characteristic specific tothe above-described vertical JFET as well as to reduce the powerconsumed in the channel region, thereby resolving the problem of heatgeneration. In order to apply a reverse bias voltage to a junctionportion between the confining region and the channel region to expandthe depletion layer into the channel region so as to achieve theoff-state, the second conductivity type impurity concentration of theconfining region needs to be higher than the first conductivity typeimpurity concentration of the channel region. Moreover, the firstconductivity type impurity concentration of the channel region can bedetermined by the required device withstand voltage. The channel regionmay be formed at a higher position than a surface of the substrate, orthe substrate surface layer itself may be the channel region.

In the above-described JFET according to the present invention, theconductive film preferably extends into the drift region.

According to the above-described arrangement, in a vertical JFET, aconductive film is provided deep into a drift (channel) path so that thecurrent that flows through the drift (channel) is reduced, and morecurrent would flow in the conductive film. Consequently, the power lossin the on-state is further reduced, and the variation at each devicesdue to the impurity concentration and the like of the drift (channel)path becomes even smaller.

In the above-described JFET according to the present invention, forinstance, a channel region width from the confining region to aconductive film in the channel region can be made smaller than adepletion layer width in the channel region due to a built-in potentialin a junction portion between the confining region and the channelregion.

According to the above-described arrangement, in the case where the gatevoltage is zero, the channel region of the first conductivity typedescribed above is pinched off by a depletion layer produced due to theabove-described built-in potential at the junction portion between thechannel region and the confining region of the second conductivity typelocated outside the channel region. The above-described conductive filmis not in contact with the source region that lies on and makes contactwith the above-described channel so that the path to the conductive filmis also shut off due to the above-described pinch-off. As a result, evena vertical JFET having a high withstand voltage and small consumed powerin the on-state can be made normally-off. Thus, the power loss in theoff-state is eliminated and application to the control of a motor isfacilitated.

In the above-described JFET according to the present invention, theconductive film is one of a semiconductor film including an impurity ofhigh concentration and a metal film.

According to the above-described arrangement, a parallel bypass of lowresistance can be conveniently provided to a channel region using ametal film of low resistance. Anything can be utilized as a metal filmas long as it can serve as an electrode material; however, it ispreferably aluminum (Al) or an aluminum alloy when ease of etching andhigh conductivity are taken into consideration.

In the above-described JFET according to the present invention, forinstance, the semiconductor thin body is an SiC substrate, and a firstconductivity type semiconductor film is a first conductivity type SiCfilm, and a second conductivity type semiconductor film is a secondconductivity type SiC film.

SiC has excellent withstand voltage and its carrier mobility is as highas that of Si, and it achieves a high saturation drift speed of thecarriers. Consequently, it becomes possible to utilize theabove-described JFET for a power high-speed switching device.

A method of manufacturing a JFET according to the present inventionincludes a step of forming a first semiconductor layer of a firstconductivity type of a concentration C1 that is lower than aconcentration Cs on a semiconductor substrate of the first conductivitytype including a first conductivity type impurity of concentration Cs (asemiconductor substrate of the first conductivity type of concentrationCs), a step of forming a second semiconductor layer of the firstconductivity type of a concentration C2 that is lower thanconcentrations Cs and C1 on the first semiconductor layer of the firstconductivity type, and a step of forming a third semiconductor layer ofthe first conductivity type of a concentration C3 that is higher thanconcentrations C1 and C2 on the second semiconductor layer of the firstconductivity type. This manufacturing method further includes a step ofproviding a mask for shielding a source region on the thirdsemiconductor layer of the first conductivity type and removing thethird semiconductor layer of the first conductivity type other than thesource region by etching, and a step of doping the second semiconductorlayer of the first conductivity type on either side of the source regionwith a second conductivity type impurity to form a second conductivitytype confining region and a second conductivity type gate region of aconcentration C4 that is higher than concentration C2.

According to this manufacturing method, the number of steps is reducedand the number of masks is accordingly reduced so that mask alignment issimplified and the manufacture of the FET is facilitated. Consequently,the yield improves and the reduction in manufacturing cost becomespossible.

In the above-described manufacturing method of the JFET according to thepresent invention, for instance, ion implantation in second conductivitytype impurity doping is preferably performed using the same mask usedfor etching of the third semiconductor layer of the first conductivitytype.

According to this manufacturing method, etching and ion implantation canbe performed using the same mask so that the number of steps is reducedand reduction in the yield due to misalignment can be avoided. As aresult, the manufacturing cost can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of an arrangement of a JFET accordingto a first embodiment of the present invention.

FIG. 2 is a diagram representing an example of a voltage in the on-stateof the JFET in FIG. 1.

FIG. 3 is a diagram representing a depletion layer formed in apinch-off-state.

FIG. 4 is a diagram representing a relation between a drain voltage anda drain current.

FIG. 5 is a diagram representing a depletion layer formed uponapplication of a high voltage in the off-state.

FIG. 6 is a diagram representing another example of a JFET similar tothe JFET according to the first embodiment.

FIG. 7 is a diagram representing a portion on the drain region side of adepletion layer formed upon application of a high voltage in theoff-state of the JFET in FIG. 6.

FIG. 8 is a diagram representing a further example of a JFET similar tothe JFET according to the first embodiment.

FIG. 9 is a cross sectional view showing a stage of forming onto asemiconductor substrate a film in which a source region is to be formedin an intermediate stage of the manufacture of the JFET shown in FIG. 1.

FIG. 10 is a cross sectional view showing a stage of patterning thesource region by RIE after the step of FIG. 9.

FIG. 11 is a cross sectional view showing a stage of doping an impurityto form a gate region and a confining region after the step of FIG. 10.

FIG. 12 is a cross sectional view of a JFET according to a secondembodiment of the present invention.

FIG. 13 is a cross sectional view showing a stage of forming an n typesemiconductor layer on an n⁺ type substrate in the manufacture of theJFET of FIG. 12.

FIG. 14 is a cross sectional view showing a stage of forming a mask on aregion where a conductive layer is to be formed and performing ionimplantation of an n⁺ type impurity on either side of the mask afterFIG. 13.

FIG. 15 is a cross sectional view showing a stage of removing theabove-described mask and forming a mask on the n⁺ type semiconductorlayer to perform ion implantation of a p⁺ type impurity after FIG. 14.

FIG. 16 is a cross sectional view showing a stage of removing the maskand forming an interposed region after the stage of FIG. 15.

FIG. 17 is a cross sectional view showing the state after havingperformed etching to form a source region and a channel region after thestep of FIG. 16.

FIG. 18 is a cross sectional view showing a stage of implanting animpurity and forming a gate region after the step of FIG. 17.

FIG. 19 is a diagram representing a depletion layer formed by applying areverse bias voltage to the JFET of FIG. 12.

FIG. 20 is a cross sectional view of a JFET according to a thirdembodiment of the present invention.

FIG. 21 is a diagram representing a depletion layer formed by applying areverse bias voltage to the JFET of FIG. 20.

FIG. 22 is a cross sectional view of a JFET according to a fourthembodiment of the present invention.

FIG. 23 is a diagram representing a depletion layer formed by applying areverse bias voltage to the JFET of FIG. 22.

FIG. 24 is a cross sectional view of a JFET according to a fifthembodiment of the present invention.

FIG. 25 is a cross sectional view of a conventional horizontal JFET.

FIG. 26 is a cross sectional view of an SIT that is a conventionalvertical JFET.

BEST MODES FOR CARRYING OUT THE INVENTION

Next, the embodiments of the present invention will be described usingthe drawings.

First Embodiment

FIG. 1 is a cross sectional view of an arrangement of a JFET accordingto the first embodiment of the present invention. In FIG. 1, a sourceregion 1 is formed in a shape of a projection protruding from a surfaceof a semiconductor substrate and includes an n type impurity of a highconcentration that largely exceeds 10¹⁹ cm⁻³ such that an ohmic contactis established with a source electrode 11 formed by Ni, for instance. Achannel region 10 includes an n type impurity at a concentration ofabout 1×10¹⁵ cm⁻³, for instance, and is formed beneath source region 1.A gate region 2 includes a p type impurity at a concentration of 10¹⁹cm⁻³, for instance, and is formed on a surface immediately below each oftwo gate electrodes 12. A confining region 5 encloses gate region 2 andis formed to a certain thickness of the semiconductor substrate suchthat channel region 10 is sandwiched from either side. Confining region5 includes the same kind of the p type impurity of the sameconcentration as the gate region. A drift region 4 makes contact withchannel region 10 at one end and is confined by confining region 5, andis formed in a spread out manner in the semiconductor substrate to acertain thickness toward the other surface of the semiconductorsubstrate, and makes contact with a drain region 3 at the other end.Drift region 4 includes an n type impurity at about 9×10¹⁶ cm⁻³, forinstance. In contact with drift region 4, drain region 3 including an ntype impurity of a high concentration, i.e., a concentration thatlargely exceeds 10¹⁹ cm⁻³, for instance, is formed exposed on the othersurface. A drain electrode 13 is formed at a position on the othersurface opposite to source electrode 11 provided on one surface. Asdescribed above, all electrodes are preferably formed by Ni, but anelectrode may be formed by some other metal film, or may be a multilayerfilm in which several kinds of metal films are formed in layers. In thefirst embodiment, each of the gate electrode, the source electrode, andthe drain electrode forms an ohmic contact with a region with which itmakes contact. The desirable impurity concentrations for each of theregions may be listed as follows:

-   Source region 1, drain region 3: n type impurity>>1×10¹⁹ cm⁻³-   Channel region 10: n type impurity=1×10¹⁵ cm⁻³-   Drift region 4: n type impurity=9×10¹⁶ cm⁻³-   Confining region 5, gate region 2: p type impurity>>1×10¹⁹ cm⁻³

As can be seen in FIG. 1, in the JFET with the structure as describedabove, there is no contact plane surface between the confining region 5and the source region 1, because the source region 1 is arranged on topof the top surface of the semiconductor substrate while the confiningregion 5 is arranged within the semiconductor substrate below the topsurface.

FIG. 2 is a diagram illustrating the respective voltages of a source, agate, and a drain in the on-state of the field effect transistor shownin FIG. 1. Normally, a source electrode is grounded, and a gate voltageis used around voltage zero which is approximately the same as a sourcevoltage. In the on-state, electrons move from source region 1 that is ann type impurity region via drift region 4 having a length of about 2 μmto 10 μm and being stretched out in a direction of thickness of asemiconductor substrate 15 and reach drain region 3.

In a case where the gate voltage that is around zero is used, when adrain voltage is set to positive and raised high, an electron flow wouldflow in channel region 10 having a range confined by confining region 5that is a p type impurity region and in drift region 4 withoutconfinement. In the on-state, there is no resistance that blocks theflow of carriers in this path so that the consumption of the powerhardly occurs. Thus, the present JFET can provide a device that excelsin withstand voltage performance with low consumed power.

When the drain voltage is raised, the potential distribution of driftregion 4 rises steeply in the vicinity of the drain region so that theelectron flow is accelerated and an electric field of a reverse bias isformed in a portion of the drift region close to the confining region,so that a depletion layer is generated toward the drift region. Thedepletion layers grow with the rise of the drain voltage, and apinch-off is established when the growth reaches a position where bothdepletion layers make contact in the drift region. When the pinch-offtakes place, the drain current does not increase even with a furtherincrease in the drain voltage and maintains a constant saturationcurrent. FIG. 3 is a diagram showing a pinch-off occurring and how adepletion layer 6 is formed in drift region 4 that is a low impurityconcentration region of a pn junction portion. The electron flow isinhibited by depletion layer 6 and the drain current becomes saturated.

FIG. 4 is a diagram representing a relation between the drain currentand the drain voltage. When the gate voltage is around zero, as thedrain voltage is increased, the drain current increases linearly. Whenthe drain voltage reaches the pinch-off voltage, however, a depletionlayer would grow from pn junction portions on either side of the driftregion toward the drift region side as described above, thereby pinchingoff the drift region and causing saturation of the drain current. Thegradient of the rise of the drain current is great in comparison withthe conventional JFET. Thus, a high current can be achieved with lowdrain voltage, and as a result, large current can be supplied withsmaller loss than in the conventional example. FIG. 4 also shows theoff-state in which the drain current hardly flows in the case where avoltage lower than Vgoff (negative) is applied as the gate voltage (itis never made lower than Vgoff by more than a certain value, however).

In such off-state, as shown in FIG. 2, a reverse bias voltage is appliedto gate electrode 12 to cause a depletion layer to be projected tochannel region 10 from a pn junction interface between channel region 10and confining region 5. The off-state is realized when the depletionlayer blocks the cross section of a path toward the other surface in thechannel region. In the off-state; as the drain voltage is raised, asshown in FIG. 5, depletion layer 6 is generated at a pn junctioninterface between confining region 5 and drift region 4 and becomesprojected toward the drift region of a low concentration. This depletionlayer withstands the voltage so that the withstand voltage performanceof the device improves.

While the control of a drain current, the ON-OFF and the like isperformed by a drain voltage and a base voltage in an SIT that is aconventional vertical JFET, as described above, the ON-OFF control isperformed by the presence/absence of formation of the above-describeddepletion layer in the field effect transistor of the present invention.As a result, it has become possible to perform the control of highvoltage and high current with certainty with the field effect transistorof the present invention.

When a high voltage is applied to a drain while the current is shut offin the off-state, depletion layer 6 is formed in a pn junction portionthat is an interface between confining region 5 and drift region 4 closeto a drain region, as shown in FIG. 5. Since this depletion layer 6withstands the voltage between the drain and the gate, a field effecttransistor with excellent withstand voltage can be achieved. Thisdepletion layer 6 is formed toward a low impurity concentration side,with the depth being greater where the impurity concentration is lower,in a manner similar to the mechanism by which the above-describeddepletion layer is formed. As shown in FIG. 5, depletion layer 6 stillhas room for growth on the drain side even when the voltage is furtherincreased from the state of FIG. 5 so that an extremely high voltage canbe endured.

Although in some cases, drain region 3 is given a structure of beingspread on a surface as shown in FIG. 1, drain region 3 may be confinedand be given a structure in which drift region 4 above the drain regionis also covered by confining region 5, as shown in FIG. 6. In the caseof the drain region and the drift region of the shapes shown in FIG. 6,when a high voltage is applied to a drain in the off-state, depletionlayer 6 that withstand the high voltage is formed as shown in FIG. 7.

In addition, the scope of the present invention also includes astructure shown in FIG. 8 in which a thickness of the confining regionis increased and drain region 3 and drift region 4 are given thestructure of being spread on a surface as shown in FIG. 1. In this case,a thickness of drift region 4 sandwiched by the confining region and thedrain region becomes thin so that a significant improvement in thewithstand voltage cannot be expected; however, the thickness of theconfining regions sandwiching the channel region is thick so that anormally-off JFET can be formed with ease.

Next, a method of manufacturing the JFET shown in FIG. 1 will bedescribed. First, as shown in FIG. 9, on an n⁺ type semiconductorsubstrate 31, an n type semiconductor layer 32, an n⁻ semiconductorlayer 33, and an n⁺ semiconductor layer 34 are successively formed.Thereafter, as shown in FIG. 10, to form source region 1, other portionsare etched and removed by RIE (Reactive Ion Etching). Thereafter, asshown in FIG. 11, p type impurity ions are implanted to form gate region2 and confining region 5. Then, Ni is formed as an electrode, and theJFET as shown in FIG. 1 is completed. The electrodes in the firstembodiment, including the gate electrode, are provided such that anohmic contact is formed. Since the impurity concentration of gate region2 is high, the formation of the ohmic contact is easy.

According to this manufacturing method, the manufacturing steps aresimplified, and the number of masks is reduced. Moreover, the chance ofmask misalignment occurring reduces as well so that the yield can beimproved.

Example Corresponding to First Embodiment

A semiconductor thin body and a semiconductor layer formed thereon wereall formed by 4H-SiC, and withstand voltage performance andon-resistance (resistance in the on-state) of a JFET having thefollowing dimensions were measured (with respect to a drift regionthickness t₁, a confining region thickness t₂, a channel region width W,see FIG. 1).

-   Drift region thickness t₁,=2.2 μm-   Confining region thickness t₂,=1 μm-   Channel region width W=10 μm

Result of Measurement

-   Voltage resistance: 380 V (gate voltage when OFF: at minus 22 V)-   On-resistance: 0.7 mΩ·cm²

As described above, from the FET of the present invention, a result ofhigh withstand voltage performance and extremely low on-resistance wasobtained. Consequently, since it achieves low consumed power with highwithstand voltage and has a simple structure, it is easy to manufactureand the manufacturing cost can be kept low.

Second Embodiment

FIG. 12 is a cross sectional view of an arrangement of a JFET accordingto the second embodiment of the present invention. A source electrode 11and a gate electrode 12 are provided on one main surface (front face) ofa semiconductor substrate, while a drain electrode 13 is provided on theother main surface (reverse face). A source region 1 is formed incontact with source electrode 11, a gate region 2 is formed in contactwith gate electrode 12, and a drain region 3 is formed in contact withdrain electrode 13, respectively. Channel region 10 is provided incontact with source region 1 and gate region 2 and controls an on-stateand an off-state of carriers by potentials of the gate region and thesource region. To bring about the on-state, zero voltage that is thesame as that applied to the source electrode or a positive voltage isapplied to the gate electrode to cause the electrons of source region 1to move toward drain region 3 having a higher potential. A drift region4 becomes a passage of electrons that are the carriers headed fromchannel region 10 to drain region 3. A width of drift region 4 may beconfined by a confining region 5 of a p type conductive region, or maynot be confined by confining region 5 as shown in FIG. 12. This JFETemployed in a power semiconductor device is used to facilitateincreasing and decreasing of the voltage and the like by providing adirect current in a pulsed manner by performing the switching of ON-OFF.A significant characteristic that the JFET for power semiconductordevice of FIG. 12 has is that it is provided with an interposed region20 that is in contact with source electrode 11 and that penetratesthrough source region 1 and protrudes into channel region 10.

Next, a method of manufacturing the JFET shown in FIG. 12 will bedescribed. First, as shown in FIG. 13, an n type semiconductor layer 32is formed on an n⁺ type semiconductor substrate 31. Thereafter, as shownin FIG. 14, a mask 45 is formed on a region where a conductive layer isto be formed, and ion implantation of an n type impurity to a highconcentration is effected on either side of the mask to form an n⁺layer. Then, as shown in FIG. 15, the above-described mask is removedand a mask 46 is newly formed on the n⁺ layer on either side, ionimplantation of a p type impurity to a high concentration is effected toform a p⁺ type conductive layer. This p⁺ type impurity region becomesinterposed region 20 as shown in FIG. 16. Next, as shown in FIG. 17, toform source region 1, other portions are etched and removed by RIE(Reactive Ion Etching). Thereafter, as shown in FIG. 18, p type impurityions are implanted to form gate region 2. Then, Ni is formed as anelectrode, and the power semiconductor device shown in FIG. 12 iscompleted. The electrodes in the second embodiment, including the gateelectrode, are provided such that an ohmic contact is formed. Since animpurity concentration of each region is high, the formation of theohmic contact is easy.

Next, the mechanism in which a depletion layer is formed when a reversebias voltage is applied between source electrode 11 and gate electrode12 to cause the off-state will be described. In FIG. 12, when a negativevoltage that is lower than the voltage applied to source electrode 11 isapplied to gate electrode 12, a reverse bias voltage is applied to aninterface of a gate region and a channel region. At this time, at theinterface of a gate region and a channel region, a depletion layer growson channel region 10 side having a low impurity concentration. Due tothe presence of interposed region 20 of the p conductivity type thatmakes contact with source electrode 11, this depletion layer 21 easilyexpands to the source electrode side with a low voltage, as shown inFIG. 19. Consequently, with a voltage that is lower than thatconventionally used, two depletion layers 21 that stretch out fromeither side of the channel region combine around the center of the widthof channel region 10 at a tip portion of interposed region 20 and form abarrier against electrons. The electrons sense a potential barrier at aboundary portion of a p type conductive region so that it is notrequisite that the depletion layers are combined, and the movement ofelectrons can be interrupted by interposed region 20 making contact withdepletion layer 21. As a result, the off-state can be realized with anegative voltage whose absolute value is smaller than that in aconventional example, and it becomes possible to achieve an even lowerloss as a power switching device.

The semiconductor substrate used for the JFET shown in FIG. 12 is an SiCsubstrate having formed thereon an SiC layer by increasing the thicknessby crystal growth. A material of the semiconductor substrate, however,is not limited to SiC, and Si, GaAs and the like may be used.

Third Embodiment

FIG. 20 is a cross sectional view showing a JFET used as a powersemiconductor device in the third embodiment of the present invention. Asignificant difference between this device and the power semiconductordevice of the second embodiment is that a plurality of interposedregions 20 are provided. A method of manufacturing the semiconductordevice shown in FIG. 20 is basically the same as the method described inthe second embodiment. When a reverse bias voltage is applied between asource electrode and a gate electrode, due to the presence of interposedregions 20, a depletion layer 21 readily stretches out toward interposedregions 20 of the source region by a reverse bias voltage that is lowerthan that of the conventional example, as shown in FIG. 21. As a result,the off-state can be realized with a voltage lower than that of theconventional example, and it becomes possible to achieve an even lowerloss as a power switching device.

Fourth Embodiment

In a JFET used for the power semiconductor device of the fourthembodiment of the present invention, the overall channel region 22includes an n⁻ layer (low impurity concentration region or portion) thathas a low impurity concentration and is disposed in contact with a gateregion 2 to facilitate the formation of a depletion layer 21 thatexpands into the channel region 22 including the low impurityconcentration portion or region, as shown in FIGS. 22 and 23. Inaddition, a tip portion of an interposed region 20 stretches out beyonda side of the gate region 2 to a position reaching a drift region 4.When a reverse bias voltage is applied to a power semiconductor devicehaving such a structure, a depletion layer 21 expands into low impurityconcentration region (n⁻ layer) of the overall channel region 22 from aninterface of the gate region and the low impurity.

Fifth Embodiment

FIG. 24 is a cross sectional view showing a JFET according to the fifthembodiment of the present invention. In this diagram, an n type impurityregion on an n type SiC substrate has an impurity concentration that isdetermined by a device voltage resistance, and also serves as a firstsemiconductor layer of a first conductivity type (n type). On a surface(front face) of an n type SiC substrate 15, an aluminum film 7 is formedfilling a groove to a prescribed height. An n type SiC film formingchannel regions 10 a and 10 b is formed on either side of aluminum film7. A height of channel regions 10 a and 10 b is set a little higher thana height of the above-described aluminum film 7. In contact with the twochannel regions 10 a and 10 b, p type SiC film 2 a and 2 b is formed onthe outer side, and gate electrodes 12 are disposed thereon. On the twochannel regions 10 a and 10 b, source regions 1 a and 1 b arerespectively formed, and source electrodes 11 a and 11 b are disposedthereon. Moreover, on the reverse face of n type SiC substrate 15, an n⁺type SiC film 3 is formed, and a drain electrode 13 is disposed thereon.Needless to say, an ohmic contact is formed between each electrode and asemiconductor layer.

In the on-state, carriers flow across the substrate in a direction ofthickness from source regions 1 a and 1 b to a drain region 3. Thus, anormally-on JFET is realized. At this time, although the current isdivided into a path via aluminum film 7 and a path via the channelregion and the n type SiC substrate, the electric resistance of thealuminum film is extremely low so that the current mainly flows on thealuminum film side. Thus, the present JFET is not affected by variationin dimension and in an impurity concentration in the channel region, andthe variation at each devices can be greatly reduced.

In the off-state, a negative voltage whose absolute value is large (−15to −25 V) is applied to a gate, and consequently, reverse bias voltagesare applied to the junction portions between channel regions 10 a and 10b and the p type regions on the outer side thereof Thus, a depletionlayer width expands mainly toward the side on which the impurityconcentration is low. When this depletion layer expands the entirechannel region, the path leading from the source region via substrate 15to drain region 3 is shut off. The height of aluminum film 7 is set tobe lower than channel regions 10 a and 10 b so that the path via thealuminum film is also shut off, and the off-state is realized.

The vertical JFET shown in FIG. 24 has high withstand performance sothat, by employing the JFET of the present embodiment, it becomespossible to provide a high voltage power device having smallcharacteristic variation at each devices.

Moreover, in FIG. 24, by making channel region width W shorter than awidth of the depletion layer due to a built-in potential of theabove-described pn junction portion, the channel region is shut off andthe off-state is realized at a gate voltage of zero. Thus, a JFET of anormally-off operation can be obtained.

While the embodiments and the example of the present invention aredescribed above, the embodiments and the example disclosed above areonly illustrative, and the scope of the present invention is not limitedby these embodiments and the example. The scope of the present inventionis indicated by the description of the claims and is further intended toinclude the meaning equivalent to the claims and all modificationswithin the scope.

INDUSTRIAL APPLICABILITY

A JFET according to the present invention can perform a high current,high voltage switching operation with a lower loss than in theconventional example. Moreover, by providing an interposed region thatmakes contact with a source electrode and that expands to a channelregion, an off-state can be realized with a reverse bias voltage whoseabsolute value is smaller than that of the conventional example, and itbecomes possible to provide a power semiconductor device of an evenlower loss as a bulk power switching device. Furthermore, by providing aconductive layer in parallel to the channel region, the on-resistancecan be brought to a low level, and the variation at each devices of theJFET can be reduced.

1. A junction field effect transistor, comprising: a gate region of asecond conductivity type provided on one main surface of a semiconductorthin body consisting of an SiC substrate; a source region of a firstconductivity type provided on said one main surface; a channel region ofthe first conductivity type that adjoins said source region; a confiningregion of the second conductivity type that adjoins said gate region andencloses and confines a range of said channel region; a drain region ofthe first conductivity type provided on an other main surface of saidsemiconductor thin body; and a drift region of the first conductivitytype that continuously lies in a direction of thickness of saidsemiconductor thin body from said channel region to said drain region;wherein: a concentration of an impurity of the first conductivity typein said drift region and said channel region is lower than aconcentration of an impurity of the first conductivity type in saidsource region and said drain region and lower than a concentration of animpurity of the second conductivity type in said confining region, saidsource region, said channel region, said drain region and said driftregion are formed of at least one first SiC film having the firstconductivity type, said gate region and said confining region are formedof at least one second SiC film having the second conductivity type, afirst conductivity type impurity concentration of said drift region ishigher than a first conductivity type impurity concentration of saidchannel region, and there is no contact plane surface between saidconfining region and said source region.
 2. The junction field effecttransistor according to claim 1, wherein said confining region confinesand encloses said gate region from an inner side of said semiconductorthin body.
 3. The junction field effect transistor according to claim 1,wherein a location and spatial extent of said gate region coincides withsaid confining region.
 4. The junction field effect transistor accordingto claim 1, wherein said source region is formed protruding from the onemain surface and said channel region is formed beneath said sourceregion in a continuous manner.
 5. The junction field effect transistoraccording to claim 1, wherein said gate region comprises two gate regionportions, said confining region comprises two confining region portions,the two gate region portions are respectively confined and enclosed bythe two confining region portions, and said channel region is disposedin contact with and between the two confining region portions.
 6. Thejunction field effect transistor according to claim 1, wherein a widthof the channel region sandwiched between two portions of said confiningregion is smaller than a thickness of a depletion layer due to abuilt-in potential in a junction portion between said confining regionand the channel region.
 7. A method of manufacturing the junction fieldeffect transistor according to and incorporating all limitations ofclaim 1, wherein said at least one first SiC film having the firstconductivity type includes a semiconductor substrate and first, secondand third semiconductor layers, and wherein said method comprises thesteps of: providing said semiconductor substrate of the firstconductivity type, in which said drain region is to be formed, includinga first conductivity type impurity of concentration Cs; forming saidfirst semiconductor layer, in which said drift region is to be formed,of the first conductivity type having an impurity concentration C1 thatis lower than said concentration Cs, on the semiconductor substrate;forming said second semiconductor layer, in which said channel region isto be formed, of the first conductivity type having an impurityconcentration C2 that is lower than said concentrations Cs and C1, onsaid first semiconductor layer of the first conductivity type; formingsaid third semiconductor layer, in which said source region is to beformed, of the first conductivity type having an impurity concentrationC3 that is higher than said concentrations C1 and C2, on said secondsemiconductor layer of the first conductivity type; providing a mask forshielding said source region on said third semiconductor layer of thefirst conductivity type, and removing said third semiconductor layer ofthe first conductivity type at an area other than said source region byetching so as to form and leave said source region remaining; and dopingsaid second semiconductor layer of the first conductivity type on twosides of said source region with said impurity of the secondconductivity type with a concentration that is higher than said impurityconcentration C2 to form said confining region of the secondconductivity type and said gate region of the second conductivity typeas said at least one second SiC film having the second conductivity typein said second semiconductor layer.
 8. The method of manufacturing ajunction field effect transistor according to claim 7, wherein saiddoping of said impurity of the second conductivity type comprises ionimplantation performed using the same mask used for etching of saidthird semiconductor layer of the first conductivity type.
 9. Thejunction field effect transistor according to claim 1, wherein saidsource region is disposed on top of said one main surface of saidsemiconductor thin body, and said confining region is disposed withinsaid semiconductor thin body extending below said one main surfacethereof.
 10. A junction field effect transistor, comprising: a gateregion of a second conductivity type provided on one main surface of asemiconductor thin body consisting of an SiC substrate; a source regionof a first conductivity type provided on said one main surface; achannel region of the first conductivity type that adjoins said sourceregion; a confining region of the second conductivity type that adjoinssaid gate region and encloses and confines a range of said channelregion; a drain region of the first conductivity type provided on another main surface of said semiconductor thin body; a drift region ofthe first conductivity type that continuously lies in a direction ofthickness of said semiconductor thin body from said channel region tosaid drain region; a source electrode located on said source region; andan interposed region of the second conductivity type that makes contactwith said source electrode and extends to said channel region; wherein:a concentration of an impurity of the first conductivity type in saiddrift region and said channel region is lower than a concentration of animpurity of the first conductivity type in said source region and saiddrain region and lower than a concentration of an impurity of the secondconductivity type in said confining region, said source region saidchannel region, said drain region and said drift region are formed of atleast one first SiC film having the first conductivity type, and saidgate region and said confining region are formed of at least one secondSiC film having the second conductivity type.
 11. The junction fieldeffect transistor according to claim 10, wherein said interposed regionis separated into at least two regions with a region of the firstconductivity type sandwiched therebetween.
 12. The junction field effecttransistor according to claim 8, wherein said channel region includes alow impurity concentration portion of the first conductivity type andanother portion within said channel region, said channel region is incontact with said confining region and said source region, and said lowimpurity concentration portion has an impurity concentration lower thana concentration of an impurity of the first conductivity type in saidanother portion of said channel region.
 13. A junction field effecttransistor, comprising: a gate region of a second conductivity typeprovided on one main surface of a semiconductor thin body consisting ofan SiC substrate; a source region of a first conductivity type providedon said one main surface; a channel region of the first conductivitytype that adjoins said source region; a confining region of the secondconductivity type that adjoins said gate region and encloses andconfines a range of said channel region; a drain region of the firstconductivity type provided on an other main surface of saidsemiconductor thin body; and a drift region of the first conductivitytype that continuously lies in a direction of thickness of saidsemiconductor thin body from said channel region to said drain region;wherein: a concentration of an impurity of the first conductivity typein said drift region and said channel region is lower than aconcentration of an impurity of the first conductivity type in saidsource region and said drain region and lower than a concentration of animpurity of the second conductivity type in said confining region, saidsource region, said channel region, said drain region and said driftregion are formed of at least one first SiC film having the firstconductivity type, said gate region and said confining region are formedof at least one second SiC film having the second conductivity type,said source region includes two source region portions and the channelregion includes two channel region portions; and further comprising aconductive film sandwiched between the two channel region portions in aposition range that is lower than a top surface level of the channelregion.
 14. The junction field effect transistor according to claim 13,wherein said conductive film extends into said drift region.
 15. Thejunction field effect transistor according to claim 13, wherein achannel region width from said confining region to said conductive filmin said channel region is smaller than a depletion layer width in saidchannel region due to a built-in potential in a junction portion betweensaid confining region and said channel region.
 16. The junction fieldeffect transistor according to claim 13, wherein said conductive film isa film selected from the group consisting of a metal film and asemiconductor film that includes an impurity of the first or secondconductivity type at a high concentration to make said semiconductorfilm conductive.
 17. The junction field effect transistor according toclaim 13, wherein said conductive film is a conductive metal film.
 18. Ajunction field effect transistor, comprising: a gate region of a secondconductivity type provided on one main surface of a semiconductor thinbody; a source region of a first conductivity type provided on said onemain surface; a channel region of the first conductivity type thatadjoins said source region; a confining region of the secondconductivity type that adjoins said gate region and encloses andconfines a range of said channel region; a drain region of the firstconductivity type provided on an other main surface of saidsemiconductor thin body; a drift region of the first conductivity typethat continuously lies in a direction of thickness of said semiconductorthin body from said channel region to said drain region; a sourceelectrode located on said source region; and an interposed region of thesecond conductivity type that makes contact with said source electrodeand that passes through said source region and stretches out to saidchannel region; wherein a concentration of an impurity of the firstconductivity type in said drift region and said channel region is lowerthan a concentration of an impurity of the first conductivity type insaid source region and said drain region and lower than a concentrationof an impurity of the second conductivity type in said confining region.19. A junction field effect transistor, comprising: a gate region of asecond conductivity type provided on one main surface of a semiconductorthin body; a source region including two source region portions of afirst conductivity type provided on said one main surface; a channelregion including two channel region portions of the first conductivitytype that adjoins said source region; a conductive film sandwichedbetween said two channel region portions in a position range that islower than a top surface level of said channel region; a confiningregion of the second conductivity type that adjoins said gate region andencloses and confines a range of said channel region; a drain region ofthe first conductivity type provided on an other main surface of saidsemiconductor thin body; and a drift region of the first conductivitytype that continuously lies in a direction of thickness of saidsemiconductor thin body from said channel region to said drain region;wherein a concentration of an impurity of the first conductivity type insaid drift region and said channel region is lower than a concentrationof an impurity of the first conductivity type in said source region andsaid drain region and lower than a concentration of an impurity of thesecond conductivity type in said confining region.